1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device having a data write load circuit and with an improved data write characteristic.
2. Description of the Related Art
A nonvolatile semiconductor memory device, particularly an EPROM whose memory cells are double gate nonvolatile MOS transistors with a floating gate and a control gate, allows data to be rewritten thereinto. Because of this feature, the EPROMs have been used in various types of computer systems. In a negative state of the memory cell, or the cell transistor, in which electrons have been injected into the floating gate, the threshold voltage of the memory cell is high. Therefore, in this state, even if a high level voltage of 5 V, for example, is applied to the control gate of the cell transistor, the transistor will not be conductive. In a neutral state where no electrons are injected into the floating gate, the threshold voltage maintains its initial low voltage. In this state, if the high level voltage is applied to the control gate, the cell transistor is conductive. If logical "1" and "0" are respectively assigned to the conductive and nonconductive states of the cell transistor, the data can be detected.
To inject electrons into the floating gate, a write or program voltage much higher than the normal power source voltage (5 V) is applied to the floating gate and the drain. The program voltage is 12.5 to 21 V, for example. Under such a high program voltage, impact ionization occurs in the channel region near the drain, to generate hot electrons. In turn, the hot electrons are injected into the floating gate. The electrons once injected into the floating gate are left in the floating gate unless a data erase operation is applied to the cell transistor. In this way, the cell transistor can store the data in a nonvolatile manner.
FIG. 1 shows a schematic diagram of an EPROM using the nonvolatile semiconductor memory cell as mentioned above. In the figure, WLl to WLm designate row lines to which the decoded row signals are supplied from row decoder 101. COLl to COLn indicate column select lines to which the decoded column signals are supplied from column decoder 102. Column select lines COLl to COLn are coupled with the gates of column select MOS transistors C1 to Cn of enhancement type (E type). These transistors are driven by the decoded column signals coming through "n" column select lines COLl to COLn. The first ends of these column select transistors C1 to Cn are connected together to node 103, while the second ends are connected to "n" column lines BLl to BLn. These column lines BLl to BLn are laid out crossing row lines WLl to WLm. Double gate memory cells M11 to Mmn are placed at the intersections of the column and row lines. The gates of these cell transistors M11 to Mmn are connected to row lines WLl to WLm, respectively. The drains are respectively connected to column lines BLl to BLn. The sources are connected together with ground voltage VS of 0 V, for example. Node 103 is connected to the source of MOS transistor 104. The drain of this transistor 104 is coupled with external program voltage VP. The gate is connected to the output node of data input circuit 105. Data input circuit 105 outputs input data DIN, which is set at the VS voltage or a high level voltage according to the logical state, "1" or "0", of the programmed data. In a read mode, sense amplifier 105 coupled with node 103 senses the data which depends on the potential at node 103.
For programming or writing data "0" into a memory cell M11, for example, the input data signal DIN output from data input circuit 105 is set at a high level voltage, and the decoded output from column decoder 102 sets column select line COLl at a high level voltage. The high level voltage DIN renders transistor 104 Conductive. The high level voltage on column select line COLl renders column select transistor C1 conductive. As a result, program voltage VP is applied to column line BLl. At this time, the decoded output signal from row decoder 101 provides a high level voltage on row line WLl, so that a high level voltage is applied to both the control gate and the drain of memory cell M11. Under this condition, impact ionization occurs in the channel region in the vicinity of the drain, to generate hot electrons. The generated hot electrons are in turn injected into the floating gate of cell transistor M11. In this way, the data write operation is performed.
For programming data "1" into memory cell M11, the input data signal DIN from data input circuit 105 is set at 0 V, or the VS potential, so that transistor 104 is rendered nonconductive. Under this condition, program voltage VP is not applied to column line BLl. Further, the floating gate of selected memory cell M11 keeps the neutral state. This state of the cell indicates the storage of data "1".
Recent semiconductor memory device formed of the nonvolatile memory cells progressively increases its memory capacity. With this, the time for programming the data into the memory cells is longer. The programming time must be reduced. To this end, in programming data, the cell transistor is generally operated in the avalanche region providing a high programming efficiency.
FIG. 2A typically shows one of the single memory cells of the EPROM of FIG. 1 and a data write circuit for writing data into the memory cell. In the circuit, the memory cell is denoted as M11. MOS transistors 104 and C1 make up the data write circuit. FIG. 2B shows data write characteristics of memory cells M11 with different channel lengths, and a load characteristic of the load circuit or the data write circuit. As shown, the data write characteristic is represented by a relationship of drain current ID versus drain voltage VD. FIG. 2B will be used mainly for explaining how the optimum operating point of the cell transistor depends on the channel length of the transistor in a data write mode. For plotting the data write characteristic curves I to V, a high level voltage was applied to the gates of MOS transistors 104 and C1, and a program high voltage was applied to the control gate of memory cell M11. Curve I indicates an ID-VD characteristic of memory cell M11. Rectilinear curve IV indicates a load characteristic of the write circuit formed of MOS transistors 104 and C1. The memory circuit is operated at the intersection A of curves I and IV. In other words, the circuit is operated with the drain voltage and the drain currents as indicated by point A. V denotes a line extending through point (VP-VTH) on the axis of abscissas and point A. VTH denotes the threshold voltage of MOS transistor 104.
In manufacturing memory devices including the MOS transistors, nevertherless, a variance in the channel lengths of the manufactured transistors is inevitable although it is within a limited range. The above optimum operating point of the memory circuit in a data program or write mode, depends greatly on the channel length of the transistor. This will be described referring to FIG. 2B. Curve II shows a data write characteristic of the memory circuit in which the cell transistor has a channel length longer than a specified value. When it is shorter, the data write characteristic varies as indicated by curve III. For writing data, the memory circuit having the cell transistor with the long channel length is operated at the intersection B of curves II and IV. Similarly, the memory circuit having the cell transistor with the short channel length is operated at the intersection C of curves III and IV. Point B resides outside the avalanche region. Therefore, an insufficient number of electrons are injected into the floating gate, leading to incorrect data programming. Point C resides in the avalanche region. At this point, however, drain current ID is very large. This indicates that the circuit operation at this point C consumes a large power.
In the MOS transistor 104, which is operated in a saturation region, drain current ID is mathematically expressed ##EQU1## where .beta. is the current amplification factor of transistor 104, VG the gate voltage, and VTH the threshold voltage. The equation (1) implies that drain current ID varies proportional to the square of (VG-VTH) which represents as a difference between gate voltage VG and threshold voltage VTH. Thus, the load characteristic curve is steep, and points B and C are greatly shifted from the optimum operating point A. The problems of the circuit when it is operated at point B or C are as already mentioned. If the load characteristic curve has a more gentle inclination as indicated by rectilinear curve V, the operating points B and C are within the avalanche region and the drain currents required are more near that for the optimum operating point A. Another cause for the steepness of the load characteristic curve is that drain current ID starts to rise at the drain voltage which is lower than program voltage VP by threshold voltage VTH.
The description of the problems of the prior art will be further continued referring to FIG. 3 showing a pattern of cell transistors of the memory device. As shown, a number of cell transistors are linearly arrayed in both row and column directions, to form a matrix array. The control gate of memory cell M11 is continuous to row line WLl made of polysilicon extending in the row direction. The source is connected through conductive interconnection wire N1 formed of impurity diffusion layer to ground potential line N2 made of aluminum Ae. The drain of the transistor is connected to column line N3 made of aluminum extending in the column direction. To reduce the area for the memory cell array on a semiconductor chip, ground lines N2 are provided one for eight memory cells, or 8 bits. The diffusion layer N1 existing between the source of each memory cell and the related ground line N2 has a resistance. The resistance depends on the location of each memory cell. In the illustrated case, as the distance of the memory cell from ground line N2 becomes longer, the resistance becomes larger. That is, the memory cell located at the mid-point of the space between adjacent two ground lines N2 has the largest resistance.
Turning now to FIG. 4, there is shown an electrical expression of the memory device or EPROM as physically patterned as shown in FIG. 3. As shown, the control gate of memory cell M11 is connected to row line WLl for receiving the output signal of row decoder 101. The drain is connected to column line N3. The source is connected to ground line N2, via source resistor R representative of the resistance of interconnection wire N1 between the source and ground line N2. Column line N3 is connected to the source of MOS transistor C1. The gate of transistor C1 is connected to column select line COLl for receiving the output signal of column decoder 102. The drain of transistor C1 is connected to the source of E type MOS transistor 104 as its load transistor. The drain of load transistor 104 is coupled with high voltage power source VP, which is for data programming. The gate of transistor 104 is connected to data input circuit DIC for providing the data of "1" or "0" to be programmed into a specified memory cell in response to an external signal. Transistors 104 and C1 make up a data write circuit for programming data into a specified memory cell. The data programming operation as described referring to FIG. 1 is correspondingly applied to the data programming operation of this circuit.
FIG. 5 shows three curves I to III. Curve I is a data write characteristic, i.e., ID-VD curve, of the memory cell M11 with a small source resistance, viz., the memory cell located closest to ground line N2, when data "0" is written into that memory cell. Rectilinear curve II indicates a load characteristic of the load circuit formed of the data write circuit. Curve III indicates the ID-VD curve of a memory cell with a large source resistance, which is most distanced from ground line N2 or at the mid-point between two ground lines N2. Cross-point A of curves I and II is an optimum operating point of this memory device when "0" is written into the memory cell. As the drain current ID as specified by the operating point A is larger, the number of hot electrons generated in the channel region near the drain of the cell transistor becomes larger. The number of electrons injected into the cell per unit time is also larger. Therefore, if the operating point of the memory circuit is placed in its avalanche region, the data writing time may be reduced.
When the ID-VD curve III of the memory cell with a large source resistance is compared with the ID-VD curve I of the memory cell, the breakdown voltage of the memory cell with a large source resistance is higher than that of the memory cell of a low source resistance, by the voltage drop corresponding to a difference between the source resistances. Therefore, when a single load circuit is used for those memory cells with different source resistances, the cross-points of the ID-VD curves and the load characteristic curve are different from one another. For example, point A is different from point B of curves II and III. The drain current for point B is smaller than that for point A. This implies that the injection charge per unit time is small, possibly leading to errors in data programming. For correct data programming, a long programming time is needed.
If the operating point of the memory circuit is set at the cross-point of the ID-VD curve of the memory cell with a low source resistance and the load curve, the data programming into the low-source-resistance memory cell can be performed correctly and for a short time. However, the high-source-resistance memory cell may suffer from errors in data programming, and a long time is needed for correct data programming. On the other hand, if the operating point is set at the intersection of the ID-VD curve of the high-source-resistance memory cell and the load curve, the drain current ID of the low-source-resistance memory cell is too large, resulting in excessive power dissipation.
As described above, the conventional memory devices involve the problems of long data write time and excessive power dissipation.